1. Field of the Invention
The invention relates to a frequency divider and related method of design, and more particularly, to a non-integer frequency divider and related method of design.
2. Description of the Prior Art
Please refer to FIG. 1 showing a circuit diagram of a noninteger frequency divider 10 disclosed in U.S. Pat. No. 6,356,123. The non-integer frequency divider 10 includes a phase shifter 12, four sets of ripple counters 14, 16, 18, 20, and a synthesizing circuit 22. The phase shifter 12 generates a first clock CLK0 and a second clock CLK90 delayed from the first clock CLK0 by 90 degrees. The ripple counters 14, 16, 18, 20 each include three serial D flip-flops, with an output end Q of each D flip-flop connected to an input end D of a next D flip-flop, and the output end Q of the last D flip-flop connected to the input end D of the initial D flip-flop via an inverter. The D flip-flops of the ripple counters 14, 18 and the ripple counters 16, 20 are rising-edge-triggered D flip-flops and falling-edge-triggered D flip-flops, respectively. This means the D flip-flops are triggered by a rising edge or a falling edge of a clock CLK, respectively. All the clock input ends CLK of the D flip-flops in the ripple counters 14, 16 receive the first clock CLK0. All the clock input ends CLK of the D flip-flops in the ripple counters 18, 20 receive the second clock CLK90. The synthesizing circuit 22 includes two XOR gates 24, 26 and an OR gate 28. Two input ends of the XOR gate 24 are connected to output ends A, B of the ripple counters 14, 20, respectively. Two input ends of the XOR gate 26 are connected to output ends C, D of the ripple counters 16, 18, respectively. Two input ends of the OR gate 28 are connected to output ends E, F of the XOR gates 24, 26, respectively. Additionally an output end of the OR gate 28 generates a target clock.
Please refer to FIG. 2 showing a waveform diagram of the first clock CLK0, the second clock CLK90, the signals at the output ends A-F, and the target clock during the noninteger frequency divider 10 operations. The ripple counters 14, 16, 18, 20 generate four divided clocks, each divided clock having a frequency being ⅙ that of the first clock CLK0 (i.e. having a period six times that of the first clock). By properly choosing the clocks (e.g. the output ends A–D of the ripple counters 14, 16, 18, 20) to input into the synthesizing circuit 22 for doubling twice (i.e. four times the frequency), the target clock with a frequency being the first clock CLK0 divided by 1.5 can be generated, so that non-integer (1.5) frequency dividing is completed.
The non-integer frequency divider 10 is required to include 12 D flip-flops and generate four divided clocks in order to synthesize the target clock. A reduction in structure and cost is required.